1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for fabricating an isolation structure.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Numerous isolation structures are formed within and/or upon a semiconductor substrate during the fabrication of an integrated circuit to separate the active devices of the circuit. Consequently, isolation structures arc sometimes referred to as the xe2x80x9cfieldxe2x80x9d or xe2x80x9cisolationxe2x80x9d regions of a device, while the device areas are sometimes referred to as the xe2x80x9cactivexe2x80x9d regions of a device. One popular isolation structure fabrication technology includes the process of locally oxidizing silicon (xe2x80x9cLOCOSxe2x80x9d). In general, LOCOS includes oxidizing portions of a silicon-based substrate in regions arranged adjacent to portions of the substrate designated for active devices of a circuit. There are several problems associated with LOCOS, however. In particular, field oxides formed from LOCOS generally grow laterally as well as vertically, forming an extension, sometimes referred to as a xe2x80x9cbird""s-beak structure.xe2x80x9d In many instances, a bird""s-beak structure can unacceptably encroach into an active region, affecting the performance of the device. Furthermore, the thickness variation of field oxide across the semiconductor topography may cause large elevational disparities between field and active regions of the device. Such topographical disparities can cause planarity problems which become more severe as critical dimensions shrink. In particular, thermal oxide growth is significantly thinner in small field regions (i.e., field areas of small lateral dimension) relative to large field regions. Such relatively thin field-oxide thicknesses produce problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as the xe2x80x9cshallow trench process.xe2x80x9d The shallow trench process is particularly suited for isolating densely spaced active devices having field regions less than one micron in lateral dimension. Such a trench process involves etching a silicon substrate surface to a relatively shallow depth, e.g., between approximately 0.2 microns and approximately 0.5 microns, and then refilling the shallow trench with a deposited dielectric. The trench is then planarized to complete the formation of the isolation structure. Such a trench process eliminates bird""s-beak and thin field-oxide growth problems. In addition, the isolation structure is fully recessed, offering at least a potential for a planar surface.
While the shallow trench isolation process has many advantages over LOCOS, such a trench process also has problems. For example, in some cases, a high level of substrate capacitance may be generated in a device that has layers within its active regions which are arranged elevationally below the shallow trench isolation structures of the field oxide regions. For example, a high level of substrate capacitance may be generated during the fabrication of a bipolar transistor which has a buried layer arranged below the transistor. Such an increase in substrate capacitance may be generated by the diffusion of impurity species during high temperature processing steps of the fabrication sequence. In particular, impurities from the layers of the active regions may diffuse into portions of the substrate arranged between such active region layers and the shallow isolation structures, increasing the substrate capacitance of the device. In general, high substrate capacitance may undesirably alter the performance of the device (i.e., reduce the maximum frequency of operation of the device).
Accordingly, it would be advantageous to develop a method for fabricating a device which prevents or reduces the generation of high substrate capacitance within a device. Alternatively stated, it would be beneficial to develop a fabrication method which inhibits the increase of substrate capacitance between layers of the active regions and field regions of the device. Such a method may additionally prevent or reduce the formation of bird""s beak and/or thin field oxide growth within field regions of the device. In addition, it would be advantageous for such a fabrication method to minimize the number of additional high temperature process steps needed to form such a device.
The problems outlined above may be in large part addressed by a method for processing a semiconductor topography. In particular, a method is provided which includes forming a relatively deep isolation structure within a semiconductor topography. In some cases, the method may include forming an isolation structure having a relatively shallow depth within a semiconductor layer of the semiconductor topography and etching an opening within the isolation structure such that an underlying portion of the semiconductor layer is exposed. In addition, the method may include etching the underlying portion of the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include forming a hardmask layer upon the semiconductor layer prior to etching the opening within the isolation structure having the shallow depth such that the trench extends through the hardmask layer. Such a hardmask layer may include a single layer of material, such as silicon dioxide or silicon nitride, in some cases. Alternatively, the hardmask layer may include multiple layers of materials. For example, in some cases, the hardmask layer may include a lower layer of silicon nitride and an upper layer of silicon dioxide. In yet other embodiments, the method may not include forming a hardmask layer prior to etching the opening within the isolation structure having the shallow depth.
In some cases, the method may include forming an oxide liner layer along the part of the semiconductor layer comprising the trench. In some cases, the method may additionally include depositing a nitride liner layer upon such an oxide liner layer. More specifically, the method may include depositing a nitride liner layer within the trench and adjacent regions of the semiconductor topography. In yet other embodiments, the method may not include depositing a nitride liner layer within the trench. In either case, the method may include depositing a first fill layer within the trench. In some embodiments, the method may include removing part of the first fill layer such that an upper surface of the first fill layer is substantially coplanar with an upper surface of the semiconductor topography arranged adjacent to the trench. For example, the method may include removing part of the first fill layer such that an upper surface of the first fill layer is substantially coplanar with an upper surface of the hardmask layer. In some cases, the method may include removing an upper portion of the hardmask layer prior to the step of depositing the first fill layer. In yet other embodiments, the method may not include removing an upper portion of the hardmask layer prior to the step of depositing the first fill layer. In any case, the method may include oxidizing an upper portion of the first fill layer arranged within the trench.
In yet other embodiments, the method may include removing part of the first fill layer such that an upper surface of the first fill layer is below an upper portion of the trench. More specifically, the method may include etching back the first fill layer such that an upper surface of the first fill layer is below an upper portion of the trench. In such an embodiment, the method may include forming a second layer within the upper portion of the trench. Alternatively stated, the method may include depositing a second fill layer upon the first fill layer. In some embodiments, the method may include removing part of the second fill layer such that an upper surface of the second fill layer is substantially coplanar with a hardmask layer arranged adjacent to the trench. Such a removal process may include polishing and/or etching the second fill layer.
Consequently, a semiconductor topography is contemplated herein which includes a first isolation structure recessed within a semiconductor layer of the semiconductor topography and a second isolation structure recessed within a portion of the first isolation structure and an underlying portion of the semiconductor layer. In some cases, the second isolation structure may include an upper portion and a lower portion having different material compositions than each other. For example, in some cases, the lower portion may include amorphous silicion or polysilicon. On the other hand, the upper portion may not include either of such silicon materials. Rather, the upper portion may include a dielectric material, such as silicon dioxide, silicon nitride, and/or silicon oxynitride, for example. In a preferred embodiment, the upper portion may include a material with substantially different etching or polishing characteristics than the lowermost material included in the hardmask layer arranged adjacent to the trench. In this manner, the hardmask layer may be used as an etch stop or polish stop layer. In some cases, the lower portion of the second isolation structure may additionally include an oxide liner layer. In some embodiments, the lower portion and the upper portion may additionally include a nitride liner layer as well. In any case, the upper portion of the second isolation structure may include a thickness substantially similar to a thickness of the first isolation structure in some embodiments. Alternatively, the upper portion of the second isolation structure may include a thickness substantially different than the thickness of the first isolation structure.
There may be several advantages to forming an isolation structure in the manner described above. For example, a device with minimal substrate capacitance may be formed. In particular, an isolation structure may be formed within a device such that the substrate capacitance of the device may not be substantially increased during the fabrication of the device. In addition, the method may not add a significant the number of high temperature process steps during the fabrication of the device. In this manner, diffusion of impurities arranged within the active regions of the device may not increase. Moreover, the formation of bird""s beak structures and thin field-oxide regions may be minimized. As a result, the reliability of a device formed from the method described herein may be higher than a device formed from conventional techniques. In addition, a semiconductor topography having a substantially planar upper surface may be formed. More specifically, the isolation structures formed from the method described herein may have substantially small and uniform step heights. In this manner, additional structures and layers may be formed within design specifications of the device.